The M68040 uses two clocks to generate timing: a processor clock (PCLK) and a bus
clock (BCLK). The PCLK signal is twice the frequency of the BCLK signal and is internally
phase-locked to BCLK. PCLK is also distributed throughout the device to generate
additional timing for additional edges for internal logic blocks and has no bearing on bus
timing. The use of dual clock inputs allows the bus interface to operate at half the speed of
the internal logic of the processor, requiring less stringent memory interface requirements.
Since the rising edge of BCLK is used as the reference point for the phase-locked loop (PLL), all timing specifications are referenced to this edge.
Mais c'est bizarre, apparemment le modèle le plus lent est à 20 MHz, et la fréquence minimale qu'il accepte c'est 16.67 MHz. Comment peut-il marche avec un oscillateur à 16 MHz ?
EDIT : ah non j'ai pigé, la vitesse indiquée correspond à la fréquence multipliée par 2, pas la fréquence d'entrée. Donc ton Medusa tourne à 32 MHz
