Ben,
J89hw.txt (la référence de nos jours) dit autre chose sur ces ports:
KTy a écrit :
($600003):
$02 -> Switches to 4 graylevels (2 bitplanes) if you wrote $f0 at $600012
$600003 -W ($FF) Bus waitstates
The TI89 hardware needs no waitstates. AMS messes with this port on
startup for compatibility with the TI92, but the battery checker
will reset it to $FF within one second.
:7 -
:6-4 Wait states =(7-n) for non-RAM accesses
:3 -
:2-0 Wait states =(7-n) for RAM accesses
($600005):
$02 -> Freezes everything (graylevels, etc) until an event happens
(keyboard)
$04 -> idem
$08 -> idem
$10 -> disturbs graylevels
$20 -> cf $02
J89hw.txt dit plus ou moins la même chose. C'est le port "idle". Freeze jusqu'à ce qu'une interruption survient. Chaque bit mis correspond à une interruption.
($600012):
$30 -> screen lines are now 32 bytes long
$10 -> 32 bytes lines + 4 graylevels (3 bitplanes following each other)
$f0 -> allows 2 bitplanes mode (cf $600003)
the lower 4 bits seem to be related with line size
$600012 -W ($3180 => 240x128 screen)
:15-14 -
:13-8 LCD logical width =(64-n)*2 bytes =(64-n)*16 pixels
The LCD controller DMA will send this many pixels to the
screen for each line (= between each RS).
(Les 8 autres bits correspondent à $600013.)
($600015):
$00 -> Triggers Int 3
$01 -> turns the screen off and freezes
$600015 RW ($1B)
[....]
:2 Trigger interrupt level 3 at OSC2/2^19 (~1 Hz on HW2)
:1 OSC2 (and OSC3?) enable (bit clear means oscillator stopped!)
:0 LCD controller DMA enable, LCD blank ("white") if =0
This bit is only examined by the hardware at the start of
each frame.
HW1: The DMA steals ~10% of the CPU bus bandwidth.
($60001c):
$f0 -> magnify the screen vertically (strange)
$30 -> idem
bit 3 seems to horizontally unmagnify the screen
$3c -> a line at the bottom of the screen
$3d -> idem
$3e -> idem at the top
$3f -> idem a bit lower
$60001C -W ($21 = 64 cycles/RS = 256 pixels/RS)
:7-6 ?-
:5-2 LCD RS (row sync) frequency, OSC2/((16-n)*8)
%1111 turns off the RS completely (used when LCD is off).
:1-0 ??? Used for sth? -- why otherwise set to %01?
Bref, ce que tu appelles "niveaux de gris matériels" me paraît être un gros abus des waitstates...
