(désolé pour ceux qui pigent queud
))
<- j'y penserai quand j'aurai un satellite a envoyer 
(allez, soyons honnêtes : il y en a quelques-uns chez Atmel aussi)
), c'est surtout pour ça (et aussi pour leur architecture qui me plaît globalement pas, même s'il y a parfois quelques bonnes idées).
(il y avait la probabilité d'occurence dans la doc, de mémoire à 4 MHz elle était quasi-nulle, mais non négligeable à 20 MHz ; mais je ne me souviens plus de la référence).
1. Doze ModeUne bonne proportion sont des bugs graves (feature inutilisable, corruption ou perte de données, risque de comportement imprévisible).
When Doze mode is enabled, any writes to a peripheral SFR can cause other updates to that register to cease to function for the duration of the current CPU clock cycle.
2. 12-bit Analog-to-Digital Converter (ADC) Module
For this revision of silicon, the 12-bit ADC module INL, DNL and signal acquisition time parameters are not within the published data sheet specifications.
3. 10-bit ADC Module
For this revision of silicon, the 10-bit ADC module DNL, conversion speed and signal acquisition time parameters are not within the published data sheet specifications.
4. DMA Module: Interaction with EXCH Instruction
The EXCH instruction does not execute correctly when one of the operands contains a value equal to the address of the DMAC SFRs.
5. DISI Instruction
The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the DISI counter decrements to zero.
6. Motor Control PWM
There is a glitch in the PWMxL signal in Single-Shot mode with complementary output. Another glitch occurs when resuming from a Fault condition in Free-Running mode with complementary output.
7. Output Compare Module
The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time.
8. Output Compare Module in PWM Mode
The output compare module will miss one compare event when the duty cycle register value is updated from 0x0000 to 0x0001.
9. SPI Module in Frame Master Mode
The SPI module will fail to generate frame synchronization pulses in Frame Master mode if FRMDLY = 1.
10. SPI Module in Slave Select Mode
The SPI module Slave Select functionality will not work correctly.
11. SPI Module
The SMP bit does not have any effect when the SPI module is configured for a 1:1 prescale factor in Master mode.
12. ECAN™ Module
ECAN transmissions may be incorrect if multiple transmit buffers are simultaneously queued for transmission.
13. ECAN Module
Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer ID register.
14. ECAN Module Loopback Mode
The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode.
15. I2C™ Module
The Bus Collision Status bit does not get set when a bus collision occurs during a Restart or Stop event.
16. INT0, ADC and Sleep/Idle Mode
ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero.
17. Doze Mode and Traps
The address error trap, stack error trap, math error trap and DMA error trap will not wake-up a device from Doze mode.
18. JTAG Programming
JTAG programming does not work.
19. UART
With the parity option enabled, a parity error may occur if the Baud Rate Generator (BRG) contains an odd value.
20. UART
The Receive Buffer Overrun Error Status bit may get set before the UART FIFO has overflowed.
21. UART
UART receptions may be corrupted if the BRG is set up for 4x mode.
22. UART
The UTXISEL0 bit is always read back as zero.
23. UART
The auto-baud feature may not calculate the correct baud rate when the BRG is set up for 4x mode.
24. UART
With the auto-baud feature selected, the sync break character (0x55) may be loaded into the FIFO as data.
25. ECAN Module
Buffers 6 and 7 may intermittently transmit the wrong message type.
26. I2C Module
A write collision does not prevent the transmit register from being written.
27. I2C Module
The ACKSTAT bit only reflects the received ACK/NACK status for master transmissions, but not for slave transmissions.
28. I2C Module
The D_A Status bit does not get set on a slave write to the transmit register.
29. Traps and Idle Mode
If a clock failure occurs when the device is in Idle mode, the oscillator failure trap does not vector to the Trap Service Routine.
30. MCLR Wake-up from Sleep Mode
An MCLR wake-up from Sleep mode does not wait for the on-chip voltage regulator to power up.
31. ECAN Module
The C1RXOVF2 and C2RXOVF2 registers always read back as 0x0000.
32. FRC Oscillator
Internal FRC accuracy parameters are not within the published data sheet specifications.
33. Quadrature Encoder Interface (QEI) Module
The QEI module does not generate an interrupt in a particular overflow condition.
34. Device ID Register
The content of the Device ID register changes from the factory programmed value.
35. SPI
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is erroneously enabled by the SPI2 module.
36. UART
The auto-baud feature measures baud rate inaccurately for certain baud rate and clock speed combinations.
37. Motor Control PWM (Faults in Latched mode)
Subsequent faults in the same timer cycle are missed during a latched fault.
38. Motor Control PWM (Fault-driven Wake-up)
Fault-driven Wake-up from Idle does not function.
39. DMA Module
DMA data transfers that are active in Single-Shot mode while the device is in Sleep or Idle mode may result in more data transfers than expected.
40. Doze Mode and Traps A DMA error trap may not be generated when the device is in Doze mode.
1. Module: ECCP
When the ECCP module is operating in Half-Bridge mode, use of a dead-band delay other than zero will have the effect of introducing an unintended pulse on the P1A and P1B signals.
2. Module: I/O (Parallel Slave Port)
The Input Buffer Full Status bit, IBF, of the TRISE register (TRISE<7>) may be inadvertently cleared, even when the PORTE input buffer has not been read.
3. Module: Core (Program Memory Space)
Performing table read operations above the user program memory space (addresses over 1FFFFFh) may yield erroneous results at the extreme low end of the device’s rated temperature range (-40°C).
4. Module: Core (Program Memory Space)
Under certain conditions, the execution of a table read instruction may yield erroneous results. This has been observed when a table read instruction and its read destination, as indicated by the Table Pointer registers, are on opposite sides of the 4000h program memory address boundary.
5. Module: Core (Program Memory Space)
Under certain conditions, the execution of some control operations may yield unexpected results. This has been observed when the following instructions vector code execution across the 4000h program memory address boundary:
• CALL
• GOTO
• RETURN
• RETLW
• RETFIE
6. Module: Data EEPROM
When reading the data EEPROM, the contents of the EEDATA register may be corrupted if the RD bit (EECON1<0>) is set immediately following a write to the address byte (EEADR). The actual contents of the data EEPROM remain unaffected.
7. Module: A/D (External Voltage Reference) and Comparator Voltage Reference
When the external voltage reference, VREF-, is selected for use with either the A/D or comparator voltage reference, AVSS is connected to VREF- in the comparator module. If VREF- is a voltage other than AVSS (which must be tied externally to VSS), excessive current will flow into the VREF- pin.
8. Module: CAN
CAN Disable mode change request is not confirmed. A CAN Disable mode request by writing ‘001’ to the REQOP bits (CANCON<7:5>) immediately changes the OPMODE bits (CANSTAT<7:5>), implying that Disable mode is accepted. This occurs even though the CAN module itself may not have switched its state.
9. Module: MSSP (All I2C™ and SPI™ Modes)
The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read.
10. Module: MSSP (SPI, Slave Mode)
In its current implementation, the SS (Slave Select) control signal generated by an external master processor may not be successfully recognized by the PIC® microcontroller operating in Slave Select mode (SSPM3SPM0 = 0100). In particular, it has been observed that faster transitions (those with shorter fall times) are more likely to be missed than than slower transitions.
11. Module: CAN
An incoming CAN message may not be saved properly to a CAN receive buffer if one of the following conditions is met:
1. Bank 15 is selected and the firmware attempts to read RXB0 or RXB1 registers while a CAN message reception is in progress.
2. Bank 15 is selected and an instruction is executed whose lower 8 bits match with one of the CAN receive buffer addresses (RXBn addresses in the range of 0xF61 to 0xF6E and 0xF51 to 0xF5D) while a CAN message reception is in progress. Some of the instruction examples are:
• 0xFF68 (NOP)
• 0xEE68 (first half of GOTO 0xD0)
• 0x0E6A (MOVLW 0x6A)
• 0x6055 (MOVF 0xF66, W)
Other instruction combinations exist.
3. The firmware attempts to access GPR (General Purpose Register) addresses between addresses 0x51 and 0x5D in the Access Bank while a CAN message reception is in progress. Some of the instruction examples are:
• MOVWF 0x57, A
• ADDWF 0x57, A
• MOVF 0x57, W, A
12. Module: Reset
It has been observed that in certain Reset conditions, including power-up, the first GOTO instruction at address 0x0000 may not be executed. This occurrence is rare and affects very few applications.
13. Module: CANUnder specific conditions, the first five bits of a transmitted identifier may not match the value in the Transmit Buffer ID register, TXBxSIDH. If the CAN peripheral detects a Start-of-Frame (SOF) in the third bit of interframe space, and if a message to be transmitted is pending, the first five bits of the transmitted identifier may be corrupted.
Zerosquare (./134) :
18. JTAG Programming JTAG programming does not work.
, et le pays du mec contacté squalyl (./140) :(tu remarqueras que dans le premier cas que j'ai cité, y'en a un paquet où il est marqué "Workaround : None" ou alors l'équivalent de "n'utilisez pas la feature en question"
si, y'a la possibilité par l'ICD, faut pas oublier que chaque fois que c'est possible, ces descriptions de bugs viennent avec des workarounds.
)squalyl (./143) :
chaque fois que c'est possible
SPM0 = 0100). In particular, it has been observed that faster transitions (those with shorter fall times) are more likely to be missed than than slower transitions.